Probabilistic-based Defect/Fault Characterisation of Complex Gates from Standard Cell Library

The need for development of new approaches for defect/fault analysis of VLSI circuit is growing and becomes even more important as we move further into the sub-micron devices. Yield loss in ICs fabrication and testing of the manufactured ICs now are major bottlenecks in the production of qualitative VLSI circuits. For instance, it is predicted that the test costs for the emerging deep submicron technologies will actually surpass the fabrication cost [1,2,4]. When new materials and processes are introduced, the new failure mechanisms are appeared and different behaviour of faulty circuits caused by defects is exhibited. It means that relative success in providing the high quality of testing by traditional test generation methods and tools cannot be guaranteed. For example, it is forecasted that the margin of error for automatic test equipment accuracy will be up to 50 percent by the year 2012 [2,3]. Such situation forces the development of new approaches for more precise and more detailed defect/fault analysis in VLSI circuits in order to decrease yield loss and to improve test quality. The necessity of precise and detailed defect/fault analysis is explained by the fact that traditional fault models (which are used by test developers) become less effective. Very popular in the test quality estimation, which are widely used by test developers, are stuck-at fault models (SAF), e.g stuck-at-0 (SA0) and stuck-at-1 (SA1) fault models. These models are used for the test preparation for coverage of physical defects in the CMOS digital ICs. Unfortunately, traditional SAF model does not accurately represent the real physical defects and as a result high SAF coverage cannot guarantee high quality of testing [5,6]. It is explained by the fact that when the test developers use SAF model only, they ignore the real behaviour of a gate in CMOS integrated circuit and SAF model does not adequately represent the majority of IC defects and new failure mechanisms in deep sub-micron technologies [6]. To replace abstract fault models like SAF by realistic defect models we need more detailed approach for defect/fault analysis.